Decoder Multiplexer Demultiplexer

This tool models decoder and multiplexing/demultiplexing networks used in digital logic design. It accepts core inputs such as word width, number of select bits, mode, and enable signals. Outputs include a truth table, output mapping, and derived equations for the chosen configuration.
Core logic is deterministic and rule-based. Required inputs include word_width, select_bits, data_inputs, and mode. Optional features support inverted enables and mixed word widths. It generates the full truth table, routing map, and algebraic expressions, ensuring consistent representations across configurations. Validation enforces that selects are within 0 to 2^n - 1 and word_width is at least 1.
Algorithms enumerate all 2^n select states and apply standard MUX/Demux rules: for a MUX, output equals the data input indexed by the select; for a Demux, the single input drives exactly one output channel. Enable handling gates outputs when present. Edge cases include missing inputs, out-of-range selects, and inconsistent data lengths; the tool returns explicit diagnostics.