VHDL Formatter

The VHDL Formatter transforms irregular VHDL source into a consistent, readable layout suitable for review and collaboration. It targets hardware engineers, RTL developers, students, and design teams who produce VHDL entities, architectures, processes, and test benches. The service accepts raw VHDL text and returns a standardized layout that reduces ambiguity during code reviews and speeds onboarding for new team members.
Conceptually, the tool performs lexical analysis to tokenize VHDL input, then applies a deterministic reformatter that preserves semantics while adjusting whitespace, indentation, and line breaks. Users can choose a style preset or customize indentation size, maximum line length, and keyword alignment. It emphasizes block delimitation (entity, architecture, process) and proper spacing around operators.
Unique value lies in combining VHDL-2008 compatible rules with preserve-comment options and non-destructive formatting that can be re-run without altering comments or pragmas. It supports common constructs like generate statements, case statements, and port maps, and can align on meaningful tokens. Use cases include pre-commit formatting, code reviews, and standardization across a team.
Core features include configurable indentation (2 or 4 spaces), wrap handling per max_line_length, preservation of comments, optional keyword alignment, alignment of begin/end blocks, and support for common VHDL-2008 constructs such as generate statements and record types. It also offers style presets (compact, expanded) and the ability to preserve user-defined pragmas. It does not verify semantics, but provides a deterministic, reproducible output ideal for code reviews and repository standards.