Verilog Code Formatter

This tool formats Verilog and SystemVerilog source to a consistent, readable style. It accepts raw HDL text and outputs a normalized version that adheres to a configurable coding standard, aiding code review, collaboration, and publication.
Conceptually, formatting follows a language-aware pipeline: tokenize input, parse into a structured representation, apply style rules, and emit reformatted code. It preserves semantics and comments while adjusting indentation, spacing, and line breaks. Features include automatic alignment of assignments, consistent block indentation, padding around operators, and line-wrapping for long statements; profiles match common industry conventions or can be customized for institutional style.
Who benefits: hardware design engineers, verification teams, educators, and students who review HDL code or prepare it for documentation. The tool reduces review time, improves consistency across a project, and supports faster onboarding by providing an agreed-upon baseline.
Core differentiators include language-aware parsing that minimizes the risk of altering logic, support for Verilog-2001/2005 and SystemVerilog subsets, non-destructive transformations, and ready-to-use output suitable for CI pipelines or batch processing. Typical use cases are pre-commit formatting, automated code reviews, and cleaning large legacy codebases before refactoring.